Verilog 学习笔记（1）

从零开始的点亮流水灯(〃￣︶￣)人(￣︶￣〃)

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Terasic DE1-SoC User Manual

Google “Terasic DE1-SoC User Manual” and download the user manual.

What are the different things we need to confgure on the DE1-SoC board in order to implement a desired digital circuit?

1. Configuring digital circuits.
2. Connect the input pins on the FPGA to the inputs of digital circuit inside of the FPGA.
3. Connect the output of the FPGA internal digital circuit to the correct output pin on the FPGA.

From Page 23, we found there are 4 push-buttons, 10 switches, 10 LEDs.
We can also find what FPGA pin is each connected to.

Later, we should tell Quartus to use 5CSEMA5F31C6.

Quartus

Install Quartus Software.
You will require a (free) license to use the included Questa simulation software. First, go here to generate an account. You will need the Microsoft Authenticator app on your phone. Once you are logged in, click on Sign up for Evaluation or Free Licenses.
For more details, watch this video on YouTube.

MyVeryFirstDigitalCiruit

Note: Verilog is not actrually a programming language.

• module:
  A module is a block of Verilog code that implements a certain functionality. Modules can be embedded within other modules and a higher level module can communicate with its lower level modules using their input and output ports.
• top-level module:
  A top-level module is one which contains all other modules. A top-level module is not instantiated within any other module.
• blocking and non-blocking:
  Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.
  Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and isspecified by a <= symbol. lt’s interesting to note that the same symbol is used as a relational operator in expressions, andas an assignment operator in the context of a non-blocking assignment.
  We can check it on Jdoodle.
  We usually use <= in always block; use = in initial block.

Now, let’s create a new project by following the steps below:

1. Click “create a new project”, set project file and project name.
2. Choose empty project, click next.
3. We’ve known that the device is 5CSEMA5F31C6, choose it.
4. Click Next.

I’d like to write a D flip-flop here. Click run.

module PosEdgeSynDFF(input D, input clk , input reset , output reg Q);
 always @( posedge clk) begin
  if ( reset )
   Q <= 1'b0;
  else
   Q <= D;
 end
endmodule

Make sure the module is top-level module (Quartus needs to know where is the entrance). One method is change the name of this module. However, we can also change the top-module name: Assignments - settings - General - Top-level entity, and then we can change its name.

Go to menu Tools - Netlist Viewers - RTL Viewer.

It gives us a high-level circuit diagram of the circuit we described using Verilog. Since it is easy to make a mistake, the RTL Viewer is one way of seeing whether Quartus understood our Verilog code the way we intended it to.

The next step is assigning pins. Click Assignments - pin planner, write pins we found in user manual.

Recompiling.

And then, we can program FPGA. Click Tools - Programmer, Processing - Auto Detect, Add/Change File. The “.sof” is in output file.

Finnally, click start.

7-segment Displays

Common Cathode			Common Anode
Num	Binary	HEX	Num	Binary	HEX
0	0111111	3F	0	1000000	40
1	0000110	06	1	1111001	79
2	1011011	5B	2	0100100	24
3	1001111	4F	3	0110000	30
4	1100110	66	4	0011001	19
5	1101101	6D	5	0010010	12
6	1111101	7D	6	0000010	02
7	0000111	07	7	1111000	78
8	1111111	7F	8	0000000	00
9	1101111	6F	9	0010000	10
A	1110111	77	A	0001000	08
b	1111100	7C	b	0000011	03
C	0111001	39	C	1000110	46
d	1011110	5E	d	0100001	21
E	1111001	79	E	0000110	06
F	1110001	71	F	0001110	0E

From user manual, we can find it is common Anode.

module 7_seg_Display(
    input [3: 0] num,
    output [6: 0] seg);
//CA 7-segments display;
//input: 4-bit wire [4'h0, 4'hF];
//output: connect to the pins of 7-seg;
    wire [6: 0] display [15: 0];
    
    assign display[0] = 7'h40;
    assign display[1] = 7'h79;
    assign display[2] = 7'h24;
    assign display[3] = 7'h30;
    assign display[4] = 7'h19;
    assign display[5] = 7'h12;
    assign display[6] = 7'h02;
    assign display[7] = 7'h78;
    assign display[8] = 7'h00;
    assign display[9] = 7'h10;
    assign display[10] = 7'h08;
    assign display[11] = 7'h03;
    assign display[12] = 7'h46;
    assign display[13] = 7'h21;
    assign display[14] = 7'h06;
    assign display[15] = 7'h0E;
    
    assign seg = display[num];
endmodule

Knight Rider

Note: It can be more complex.

module Knight(
    input CLOCK_50,
    output [9: 0] LEDR);
    
    wire [9: 0] ms;
    
    reg [25: 0] count;
    initial count = 26'd0;
    
    assign ms = count/50000;
    
    reg [9: 0] LED;
    reg [1: 0] state = 0;
    reg [1: 0] next_state = 0;
    
    initial LED = 0;
    always @(*) begin
        state <= next_state;
        case(state)
            0: begin
                case(ms/100)
                    0: LED <= 10'b0000000001;
                    1: LED <= 10'b0000000010;
                    2: LED <= 10'b0000000100;
                    3: LED <= 10'b0000001000;
                    4: LED <= 10'b0000010000;
                    5: LED <= 10'b0000100000;
                    6: LED <= 10'b0001000000;
                    7: LED <= 10'b0010000000;
                    8: LED <= 10'b0100000000;
                    9: begin 
                            LED <= 10'b1000000000;
                        end
                    default: LED <= 0;
                endcase
            end 
            1: begin
                case(ms/100)
                    0: LED <= 10'b1000000000;
                    8: LED <= 10'b0000000010;
                    7: LED <= 10'b0000000100;
                    6: LED <= 10'b0000001000;
                    5: LED <= 10'b0000010000;
                    4: LED <= 10'b0000100000;
                    3: LED <= 10'b0001000000;
                    2: LED <= 10'b0010000000;
                    1: LED <= 10'b0100000000;
                    9: begin 
                            LED <= 10'b0000000001;
                        end
                    default: LED <= 0;
                endcase
            end
            default: state <= 0;
        endcase
    end
    assign LEDR = LED;
    
    always @(posedge CLOCK_50) begin
        //count <= (count < 26'd50_000_000)? (count + 1'd1): 1'd0;
        if(count < 26'd50_000_000)
            count <= count + 1'd1;
        else begin
            count <= 1'b0;
            next_state <= next_state + 1'b1;
            //next_state = (next_state < Num) ? next_state + 1'b1 : 1'b0;
        end
    end
    
endmodule

We can see pin assignments in the “.qsf” file. We can also download this DE1_SoC.qsf, go to Assignments - Import Assignments and choose this file.

Create a Synopsys Design Constraints file (New - Other files - Synopsys Design Constraints file), and place this line.

create_clock -period 20 [get_ports CLOCK_50]

$5 \times 10^7 Hz = 2 \times 10^{-8} s = 20 ns$

Finally, run and program.